This invention relates to a data processing apparatus, and more particularly to a method of clock signal supply control suitable for application to a data processing apparatus including an LSI (a large scale integrated circuit) consuming a small amount of power.
The progress of technology in the field of semiconductors in recent years is very remarkable. Especially, the progress of technology in the field of MOS (metal oxide semiconductor) devices is quite remarkable. With the progress of the MOS technology, semiconductor circuit elements of smaller sizes and reduced dimensions are available, and it is now possible to integrate many circuits on a square chip which is as small as several millimeters on a side.
However, such a chip which has a high integration density or operates at a high speed requires increased power consumption per unit area, and the dissipation of heat from the elements is an important problem.
In view of the above problem, the so-called C-MOS (complementary MOS) device is now highlighted since this device consumes power only during the changing time of signal levels. By virtue of such low power consumption of the C-MOS device, power can be supplied to the device from a battery in the event of power failure. Further, because of the low power consumption, power may be exclusively supplied to the C-MOS device from a battery.
The present invention concerns a method of clock signal supply control for the purpose of further reducing the power consumption of such a C-MOS device.
With the decrease in the size of the device, the power consumption per unit area or power consumption per unit volume tends to increase although the absolute value of consumed power may be small. Therefore, reduction of the power consumption is an important problem.
An electronic desk calculator is a familiar example of a device which is designed so that, when it is left in a condition in which the power source is turned on, the power source is automatically turned off upon lapse of a predetermined period of time after it has been left in the on-condition. Thus, the automatic turning-off of the power source upon lapse of the predetermined period of time can prevent wasteful consumption of power supplied from the power source. However, this effort is limited to the saving of power of the power source by turning off the power source during the period of time in which the desk calculator is left in an inoperative condition without any use. In order to further reduce the power consumed by the device, it is preferable to turn off the power source and then to restore the power supply depending on the state of the device. Such demands are now progressively increasing.
As a known example most analogous to the present invention, there is Japanese Patent Application Laid-open No. 104272/79 entitled "COMPLEMENTARY MOS LOGIC CIRCUITS" (laid open on Aug. 16, 1979). This laid-open application relates to a logic circuit, and more particularly to a circuit for operating a logic circuit composed of complementary MOS gates, with further reduced power consumption.
Describing the practical aspect of the subject matter disclosed in the cited application, a clock inhibit signal is generated from the logic circuit composed of the MOS gates during the period of time in which the logic circuit does not make its logical operation, and this clock inhibit signal is used to control passage of an externally supplied clock signal so as to inhibit application of the external clock signal during the non-operating period of the logic circuit.
It is the intention of the feature dislosed in the cited application to inhibit application of the external clock signal during the non-operating period of a specific logic circuit. The cited application discloses only that the clock signal is controlled by a signal or a non-operation signal indicative of the fact that the specific logic circuit has ceased to operate. While the present invention contemplates to positively reduce the power consumption of such a device, that is, to stop supply of a clock signal by an instruction word, such a description is not found anywhere in the cited application.
There is also U.S. Pat. No. 3,919,695 (issued Nov. 11, 1975) entitled "ASYNCHRONOUS CLOCKING APPARATUS". The apparatus disclosed in this U.S. patent comprises independent clock circuits provided in a plurality of functional units respectively and means for varying the clock cycle.